The present invention is directed to the partial reconfiguration of programmable gate arrays, in general, and more particularly, to a bus macro and a method of partially reconfiguring a programmable gate array having a plurality of circuit designs which communicate among each other through routing between their separate and independent areas of the array using a bus macro.
In the past, field programmable gate array (FPGA) architectures accommodated only configuration of the entire array. Accordingly, with each change in a design and/or the addition of a design, a whole new bit stream had to be generated for configuring or programming the whole FPGA. Recently, however, new FPGA architectures were developed, like the Virtex(copyright) series manufactured by Xilinx(copyright), for example, that accommodated a partial reconfiguration even down to an information frame level. For a more detailed understanding of configuration and partial configuration of FPGAs reference is made to two Xilinx(copyright) application notesxe2x80x94(1) xe2x80x9cVirtex Series Configuration Architecture User Guidexe2x80x9d, XAPP151 (v1.5), Sep. 27, 2000, and (2) xe2x80x9cStatus and Control Semaphore Registers Using Partial Reconfigurationxe2x80x9d, by Nick Camilleri, XAPP153 (v1.0), Jun. 7, 1999 which are incorporated by reference herein in their entirety.
With the new architectures, bit streams may be generated piecemeal for configuring portions of an FPGA with a plurality of different designs. But, obstacles remain in connection with fully implementing partial reconfiguration for all cases. Currently, only simple designs may take advantage of partial reconfiguration, like, for example, a design that has the same routing configuration and look up table (LUT)/flip flop (FF) usage as the designs already configured within the FPGA or a design that does not include interdesign routing, i.e. routing across the virtual borders between separate design areas of the array. Accordingly, one obstacle to overcome is how to handle the partial reconfiguration of designs with different interdesign routing configurations.
In the Xilinx(copyright) series of Virtex FPGAs, the routing configuration which controls the routing throughout a design and across the virtual boundary to another design is embedded within each design. More specifically, FIG. 1 illustrates the programming structure of the architecture of an FPGA, like the Virtex series, for example. In this programming structure example, the FPGA includes a plurality of columns, with each column divided into a number of frames. Each frame is essentially 1 bit wide by N bits long and extends the full length of a column. A xe2x80x9cshadow registerxe2x80x9d within each column having the same capacity as a frame of the column accepts data loaded into the FPGA destined for one of the frames of the particular column and temporarily buffers the data until it may load it into the designated frame without interrupting substantially operation of the FPGA. In FIG. 1, each column area is distinct and separate from the other column areas. For example, input/output block (IOB) frames of a column are programmed to control input/output routing and configuration, but do not involve configuration logic block (CLB) frames or block random access memory (BRAM) frames. Likewise, BRAM frames are programmed with data and routing configuration that do not involve CLB and IOB frames.
The CLB frames contain programmed design information within that particular column of an Mxc3x97N FPGA, where M and N are the number of rows and columns of CLBs within the FPGA, respectively. With the current programming structure of FPGAs, it is a rather complex and difficult operation to program partially a separate and independent area of CLB columns for a particular design which includes interdesign routing. Each design that is routed for a particular area of CLB columns does not know how the other designs of the CLB columns were routed. So, if communication to another design is attempted through partial reconfiguration of a particular design area, the routing will vary and may not connect correctly with existing interdesign routing. Accordingly, for partial reconfiguration, there is a problem that arises when multiple designs are programmed into an FPGA with different interdesign routing structures as will be explained in greater detail herebelow.
A simple example of an FPGA that is to be configured with two designs A and B split into two areas that are separate and isolated from each other is shown in FIG. 2. Designs A and B have interdesign routing. Referring to FIG. 2, the left side columns of the FPGA may be programmed with a design A which may have multiple representations and variants referred to as A1, A2, . . . A(N). Similarly, the right side columns of the FPGA may be programmed with a design B which may also have multiple representations and variants referred to as B1, B2, . . . , B(N). Currently, in order to accommodate the interdesign routing between the A and B designs, designs A and B are combined together into one top level comprehensive design using Verilog programming language, for example, and compiled together to render a combined bit stream for configuring the FPGA. Accordingly, with each change to a different version of design A or design B or both designs, a new combined design would have to be programmed into a comprehensive verilog design which is then compiled for configuring the FPGA. Thus, a large number of combined design permutations of designs A and B would be needed to satisfy all of the possible variants of each design.
It is preferred that only one design for A and one design for B be loaded at a time by partial reconfiguration of the FPGA. In this manner, with each variant of a design, either A or B or both, the FPGA may be reprogrammed with one design at a time by partial reconfiguration without affecting the programmed area of the other design. In addition, the area of the FPGA being partially reconfigured with the new design variant may be reduced in size and the FPGA may continue to operate throughout the reconfiguration process. Moreover, only the number of design variants of each design may be libraried for configuring the FPGA. However, except for special cases as explained herein above, partial reconfiguration presents problems for designs with interdesign routing. For example, if a new design variant A2 is loaded into the FPGA by partial reconfiguration, it over-writes the previous design variant A1 that was stored in the columns of the left hand side thereof, thus possibly causing a routing disconnect between designs A and B. The same procedure may be performed for the variants of design B in the right hand columns with the same problem possible. It is desired to have the FPGA partially reconfigured in such a way to permit loading of designs A and B independent of one another without disturbing the routing therebetween. In practice, partially reconfiguring the FPGA in this manner is not easily achievable due primarily to the software limitations accommodating programming of the frames of the interdesign routing as mentioned above.
The present invention overcomes the drawbacks described herein above regarding the current architecture of FPGAs and permits partial reconfiguration of an FPGA with multiple designs having interdesign routing configurations.
In accordance with one aspect of the present invention, a bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed into the FPGA comprises: at least one row of bus lines disposed within the FPGA between at least two design areas; a first set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from a first design area to a second design area of the FPGA according to a first routing configuration embedded in the first design area; and a second set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from the second design area to the first design area of the FPGA according to a second routing configuration embedded in the second design area.
In accordance with another aspect of the present invention, a method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA comprises the steps of: designating at least one row of bus lines as a routing resource between at least two design areas of the FPGA; creating a first routing configuration for a first design for controlling a routing of signals over the designated at least one row of bus lines from the first design area to a second design area of the FPGA, the first design including the first routing configuration; creating a second routing configuration for a second design for controlling a routing of signals over the designated at least one row of bus lines from the second design area to the first design area of the FPGA, the second design including the second routing configuration; and partially reconfiguring the first and second design areas of the FPGA with the first and second designs, respectively, using the first and second routing configurations thereof.